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IRS2609DSPbF
Supply Capacitor: It is recommended to place a bypass capacitor (C IN ) between the V CC and COM pins. A ceramic 1 μF ceramic
capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce
parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node;
it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize
the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance.
However, where negative V S spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a
resistor (5 or less) between the V S pin and the switch node (see Figure 22), and in some cases using a clamping diode between
COM and V S (see Figure 23). See DT04-4 at www.irf.com for more detailed information.
Figure 22: V S resistor
Figure 23: V S clamping diode
Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to the HVIC:
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VCC pin voltage = 0V AND
VS or VB pin voltage > 0
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current conduction
path is created between VCC & VB pins, as illustrated in Fig.24 below, resulting in power loss and possible damage to the HVIC.
Figure 24: Current conduction path between VCC and VB pin
Relevant Application Situations:
www.irf.com
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